Programmable logic devices (PLDs) are used in a wide variety of applications and, as the PLDs have grown in complexity, are increasingly relied upon to perform various functions. For example, a PLD (e.g., a field programmable gate array (FPGA) or a complex programmable logic device (CPLD)) may provide high-speed serializer/deserializer (SerDes or SERDES) channels and their associated programmable physical coding sub-layer (PCS) logic for communication applications.
A conventional approach for programming the SERDES channels uses the PLD's configuration memory cells to control all of the SERDES/PCS settings. However, a PLD reconfiguration (e.g., with a different bitstream) is then required for every SERDES/PCS setting change, which may be particularly burdensome for dynamic adjustments of SERDES/PCS settings (e.g., during the prototyping phase).
Another conventional approach uses byte-based register files (e.g., accessed via a system bus) to control all SERDES/PCS settings. For example, the SERDES/PCS settings may be programmed or modified or verified by system bus write/read transfers during and after bitstream downloading, with each byte of register file having a unique address and accessed individually. However, this approach requires multiple bus transfers of the same data to different addresses if a group of SERDES channels or all of the SERDES channels require the same settings.
As a result, there is a need for improved techniques for implementing input/output circuits and configuring input/output settings, such as for example SERDES/PCS settings.